This book gives a throughout introduction to logic design (also in relation to hardware definition languages) and computer architecture. A bit of the physical foundations is also described, but on a very shallow level. The climax of the book is section 7.5 in which a pipelined CPU is schematically constructed that implements the MIPS instruction set architecture.

The book is carefully written and good to understand. It has an appealing layout, by which I mainly mean that meaningful figures are provided where they make sense educationally. It contains many exercises which are appropriate for the material covered.

On the downside, I find the description of "Memory" not as throughout as I had hoped. For example, a throughout schematic of DRAM is never provided and only cursory explanations are given. Until chapter 8 it is assumed that memory can be accessed in one clock cycle, and it is not worked out how a CPU implements logic to wait for memory.

In chapter 8, section 8.1 then tackles "Caches", but unfortunately not in the context of the overall CPU microarchitecture. The same holds for Section 8.2 which deals with virtual memory; here I miss a connection to the OS. Section 8.3 examines IO-devices in a very superficial and fast-paced way, from which I could not learn much. All in all, I found chapter 8 the weakest. ( )